1. Field of the Invention
The present invention relates in general to the field of computer networks and distributed computer systems, and in particular to a method and an arrangement for exchanging message data in a distributed computer system. Still more particularly, the present invention relates to a data processing program and a computer program product for performing the method for exchanging message data in a distributed computer system.
2. Description of the Related Art
Existing PCI adapters running their own operating system are controlled by proprietary protocols. Each new adapter gets a new control path, with new designed data transfer protocols.
In a related art embodiment of a distributed computer system, a first computer system is acting as a sending hardware system and a second computer system is acting as a receiving hardware system to exchange data, wherein the sending hardware system and the receiving hardware system are coupled via a non-transparent bridge unit. The sending hardware system includes a first central processing unit (CPU) and a first memory system with a remote metadata buffer and a first memory region and the receiving hardware system includes a second central processing unit (CPU) and a second memory system with a message data buffer and a second memory region. The receiving hardware system transfers an ownership of the message buffer to the sending hardware system and the sending hardware system manages the static message buffer of the receiving hardware system. The sending hardware system tells the receiving hardware system where data has been stored in the message buffer. Then the receiving hardware system copies the data from that position to the target memory position inside the second memory region of the second memory system. Thus two copy operations are needed on the receiving hardware system side.
In Patent Application Publication US 2003/0041176 A1 “Data transfer algorithm that does not require high latency read operations” by Court et al. a mechanism for the controlled transfer of data across LDT and PCI buses without requiring any high latency read operations is disclosed. The disclosed mechanism removes the need for any read accesses to a remote processors memory or device registers, while still permitting controlled data exchange. This approach provides significant performance improvement for systems that have write buffering capability. A described data transfer apparatus includes a first processor and a second processor in communication with the first processor via a data exchange path. Each processor includes a set of four counters that are organized as two pairs, where one pair of counters is used by a transmit channel via a data exchange path and a second pair of counters is used by a receive channel via a data exchange channel. The processors reserve remote buffers to coordinate the exchange of data packets by writing to the counters remotely and reading from the counters locally, wherein the processors exchange the data packets with posting operations and without resort to remote read operations.